Embodiments of the present invention relate to digital circuits, and more particularly, to cache memory cells.
As device technology scales to smaller dimensions, sub-threshold leakage current may present problems if circuits are not properly designed. The increase in sub-threshold leakage current may have a negative impact on circuit robustness, particularly for many single-ended caches in which each bit line is shared by a plurality of memory cells.
As an example, a portion of a cache circuit is shown in FIG. 1, where memory cell 102 is connected to local bit line 104. In practice, there will be other local bit lines, as well as other memory cells connected to local bit line 104, but for simplicity, only one local bit line is shown, and only one memory cell is shown connected to local bit line 104. Memory cell 102 comprises cross-coupled static inverters 106 to store binary data, read-pass transistor 108, and read-access transistor 110. For simplicity, a write port is not shown.
During a pre-charge phase, clock signal xcfx86 is LOW so that pullup transistor 114 is ON to charge local bit line 104 HIGH. The signal driving the gate of read-access transistor 110, referred to as a read-select signal, is a dynamic signal, so that it is LOW during a pre-charge phase. During an evaluation phase, clock signal xcfx86 is HIGH so that pullup transistor 114 is OFF.
Read operations are performed during an evaluation phase. For convenience, the data stored in a memory cell is taken as the logical value of the gate of the corresponding read-pass transistor, so that a logical xe2x80x9c1xe2x80x9d corresponds to a HIGH gate voltage and a logical xe2x80x9c0xe2x80x9d corresponds to a LOW gate voltage. Consider the case in which a read operation is performed on memory cell 102. The read-select signal driving read-access transistor 110 is HIGH. Local bit line 104 is pulled LOW if memory cell 102 stores a logical xe2x80x9c1xe2x80x9d. If, however, the stored data is a logical xe2x80x9c0xe2x80x9d, then local bit line 104 will not be pulled LOW by memory cell 102, in which case half-keeper 112 is designed to maintain local bit line 104 HIGH.
Consider a scenario in which all memory cells connected to local bit line 104 store a logical xe2x80x9c1xe2x80x9d. If during an evaluation phase no read operations are performed on the memory cells connected to local bit line 104, then the cumulative effect of sub-threshold leakage current through each read-access transistor may discharge local bit line 104 LOW or close to LOW. Consequently, power must be expended to charge local bit line 104 HIGH during the next pre-charge phase, for otherwise an erroneous read operation may occur in the next evaluation phase.
Consider another scenario in which memory cell 102 stores a logical xe2x80x9c0xe2x80x9d, and all other memory cells connected to local bit line 104 store a logical xe2x80x9c1xe2x80x9d. Furthermore, suppose that during an evaluation phase a read operation is performed on memory cell 102. The cumulative effect of sub-threshold leakage current in the other memory cells connected to local bit line 104 may be sufficient to pull local bit line 104 to LOW, or close enough to LOW, so that the stored data in memory cell 102 is incorrectly read as a logical xe2x80x9c1xe2x80x9d.
For some prior art circuits, half-keeper 112 is sized large enough so that local bit line 104 is not discharged by sub-threshold leakage current. However, a larger half-keeper increases contention when a local bit line is pulled LOW by a memory cell. This contention may degrade the performance of the cache. Furthermore, sub-threshold leakage current causes power to be expended to maintain local bit line 104 HIGH during a pre-charge phase, or to maintain local bit line 104 during an evaluation phase under the second scenario considered above.